Researchers from multiple universities have developed Gemini, a comprehensive framework for optimizing performance, energy efficiency, and monetary cost (MC) in DNN chiplet accelerators. Gemini employs innovative encoding and mapping strategies, a dynamic programming-based graph partition algorithm, and a Simulated-Annealing-based approach for optimization. Experimentation demonstrates Gemini’s superiority over existing state-of-the-art designs.
Researchers from Tsinghua University Unveil ‘Gemini’: A New AI Approach to Boost Performance and Energy Efficiency in Chiplet-Based Deep Neural Network Accelerators
Practical Solutions and Value:
Researchers from multiple universities have addressed the challenge of designing large-scale DNN chiplet accelerators, focusing on optimizing monetary cost (MC), performance, and energy efficiency. The complexity arises from the interplay of various parameters, including network-on-chip (NoC) communication, core positions, and different DNN attributes. It is crucial to explore a vast design space for effective solutions.
Currently, existing DNN accelerators need help in achieving an optimal balance between MC, performance, and energy efficiency. They introduced the architecture and mapping co-exploration framework for DNN chiplet accelerators, Gemini. Gemini employs a novel encoding method to define low-power (LP) spatial mapping schemes, allowing for an exhaustive exploration of hidden optimization opportunities. The framework utilizes a dynamic programming-based graph partition algorithm and a Simulated-Annealing-based (SA-based) approach for optimization.
Gemini’s mapping component uses the SA algorithm with five operators tailored to efficiently explore the LP spatial mapping space. These operators include modifying partition attributes, swapping cores within computational groups (CG), and adjusting DRAM-related attributes. The framework dynamically optimizes data transmission, intra-core dataflow, and D2D link communication, contributing to enhanced performance and energy efficiency. The evaluation process involves assessing MC, energy consumption, and delay through an Evaluator module.
The architecture aspect of Gemini provides a highly configurable hardware template, enabling precise evaluations for performance, energy, and MC. The proposed framework’s experiments showcase that the explored architecture and mapping scheme outperforms existing state-of-the-art (SOTA) designs like Simba with Tangram mapping. Gemini also achieves significant improvements with only a marginal increase in MC, demonstrating its effectiveness in co-exploring the architecture and mapping space.
In conclusion, the Gemini framework offers a comprehensive solution to the intricate challenges of designing DNN chiplet accelerators. The experiments not only validate Gemini’s effectiveness but also shed light on the potential benefits of chiplet technology in architecture design. Overall, Gemini stands out as a valuable tool for researchers and practitioners aiming to design high-performance and energy-efficient DNN accelerators.
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