Researchers from MIT and NVIDIA have devised two techniques to accelerate the processing of sparse tensors in machine learning models. The first technique, called HighLight, efficiently handles diverse sparsity patterns by breaking them down into simpler ones and forming a hierarchy. The second technique, named Tailors and Swiftiles, optimizes tile size and reduces computational resources, doubling speed while halving energy consumption compared to existing accelerators. These techniques exploit zeros in tensors to save memory and computation.
Researchers from MIT and NVIDIA Developed Two Complementary Techniques to Boost Machine Learning Performance
Researchers from MIT and NVIDIA have developed two techniques that can significantly improve the speed and performance of machine learning tasks. These techniques focus on optimizing the processing of sparse tensors, which are multi-dimensional arrays used to store and organize data in machine learning models.
Technique 1: HighLight
The first technique is a hardware accelerator called HighLight. It efficiently handles diverse sparsity patterns by using hierarchically structured sparsity. This method breaks down numbers into smaller groups, each following a simple pattern. These smaller groups are then combined into larger groups, forming a hierarchy. HighLight can find and skip zeros more efficiently, resulting in better energy efficiency compared to other approaches.
Technique 2: Tailors and Swiftiles
The second technique focuses on optimizing data movement and processing on computer chips. By leveraging sparsity, researchers aim to use larger tiles (chunks of data) that fit into the chip’s memory buffer. They use an overbooking technique to allow for an increase in tile size, accommodating most tiles with enough zeros to fit into the buffer. Excess data are pushed out of the buffer, and only the displaced data are retrieved without processing the entire tile again. This technique, called Tailors, is combined with Swiftiles, which efficiently determines the optimal tile size. Together, they double the speed and reduce energy consumption compared to existing hardware accelerators.
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