Practical Solutions for Efficient Hardware-Software Co-Design for AI with In-Memory Computing and HW-NAS Optimization
Introduction
The rapid growth of AI and complex neural networks drives the need for efficient hardware that suits power and resource constraints. In-memory computing (IMC) is a promising solution for developing various IMC devices and architectures. Designing and deploying these systems requires a comprehensive hardware-software co-design toolchain that optimizes across devices, circuits, and algorithms.
AI Processing Capabilities for IoT
The Internet of Things (IoT) increases data generation, demanding advanced AI processing capabilities. Efficient deep learning accelerators, particularly for edge processing, benefit from IMC by reducing data movement costs and enhancing energy efficiency and latency, necessitating automated optimization of numerous design parameters.
Hardware-Aware Neural Architecture Search (HW-NAS)
Researchers have explored hardware-aware neural architecture search (HW-NAS) to design efficient neural networks for IMC hardware. This approach optimizes neural network models by considering IMC hardware’s specific features and constraints, aiming for efficient deployment. Key considerations in HW-NAS include defining a search space, problem formulation, and balancing performance with computational demands.
Advantages of IMC
In traditional von Neumann architectures, the high energy cost of transferring data between memory and computing units remains problematic despite processor parallelism. IMC addresses this by processing data within memory, reducing data movement costs, and enhancing latency and energy efficiency. IMC systems use various memory types like SRAM, RRAM, and PCM, organized in crossbar arrays to execute operations efficiently.
Deep Learning Techniques for IMC
HW-NAS for IMC integrates four deep learning techniques: model compression, neural network model search, hyperparameter search, and hardware optimization. These methods explore design spaces to find optimal neural network and hardware configurations, aiming for efficient performance within given hardware constraints.
Challenges and Future Research
While HW-NAS techniques for IMC have advanced, several challenges remain. Future research should aim for frameworks that optimize software and hardware levels, support diverse neural networks, and enhance data and mapping efficiency. Combining HW-NAS with other optimization techniques is crucial for effective IMC hardware design.
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