Hardware designers spend countless hours writing RTL, debugging simulations, and iterating on testbenches. The manual cycle is slow, error‑prone, and scales poorly as designs grow more complex. Teams often rely on one‑shot code generation tools that produce syntactically correct Verilog but fail to meet functional correctness because they ignore cycle‑level behavior, reset handling, width mismatches, and simulator feedback. Consequently, integration delays increase, verification resources are strained, and product timelines slip.
A practical answer is to treat hardware design as a repository‑level evolution problem. Start with a concise structured Markdown harness that captures the design goal, domain knowledge, evaluator specification, and acceptance predicate. From this harness a bootstrap agent creates an isolated git worktree—a project pack. The agent then enters a hands‑free loop: it plans an edit, modifies the worktree, runs compilation, simulation, coverage, and assertion checks, and lets an acceptance gate decide whether to commit the change or log a failure. Only changes that pass executable evidence become permanent commits, while rejected attempts are stored as negative examples for learning. Git itself becomes the experience buffer, providing cheap traceability via diffs and commit notes.
Because the loop reuses a persistent model session, most tokens are served from prompt cache; only the current diff and evaluator output incur fresh cost. This approach reduces the need for constant human intervention, converges on 100 % pass rates across diverse RTL benchmarks, and exposes where token consumption concentrates—primarily in long‑tail tasks like code completion. By shifting from one‑shot prompts to iterative, evidence‑driven repository evolution, hardware teams can accelerate design closure, improve verification coverage, and free engineers to focus on higher‑level architecture rather than low‑level debugging.
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